Oregano Systems Design und Consulting GmbH (ore, AUT)

Mohsgasse 1, 1030 Wien - Austria

Phone +43 676 84 31 04 200 / Fax +43 8900 940 12

http://www.oregano.at



Oregano Systems Design and Consulting Ltd. offers both IP cores and design services for FPGAs and Embedded Systems focused primarily but not exclusively on industrial electronics and telecom applications. Located in Vienna, Austria, the company was founded in 2001 as a spin-off from the Vienna University of Technology, where the fundamental technology for highly accurate and fault tolerant clock synchronization via Ethernet networks was developed. Aside from its IP core business, the Oregano Systems design team offers full design support ranging from simple interface adaptations to complete SoC and Embedded Systems design. Currently, the Oregano Systems design team includes over ten design engineers, with more than one hundred years of combined experience in the area of FPGA, ASIC and mixed signal embedded system design.


Members:

Dipl.-Ing. Nikolaus Kero senior researcher

keroeoregano.at

Phone: +43 676 843104300

Received his Dipl.-Ing. degree in electrical engineering (communication engineering) from the Vienna University of Technology (TU-Wien), Vienna, Austria in 1985. For more than fifteen years he lead ASIC_Design activites at the Vienna University of Technology. Since 2001, he is one of two owner-managers of Oregano Systems Design and Consulting GmbH. Special interests: Embedded system design, PCB design, network-based clock synchronization, project management

Dipl.-Ing. Christian Eckel researcher

eckeloregano.at

Phone: +43 676 843104450

Christian Eckel was born in Vienna, Austria, in 1974. He received the Dipl.-Ing. degree in electrical engineering from the Vienna University of Technology, Vienna, Austria, in 2003. From 2002 to 2005 he was employed at the Institute of Computer Technology at the Vienna University of Technology. Since 2005 he is with Oregano Systems Design and Consulting GmbH. His major areas of interest are system design for FPGA based high performance data processing. Special interests: system design, high speed FPGA design



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